1. Field of the Invention
The invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching (FFS) mode liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules.
In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling the light transmittance of the liquid crystal molecules.
Since the LCD device including thin film transistors as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent resolution in displaying moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and a thin film transistor, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode and thus has excellent properties of transmittance and aperture ratio. Since the AM-LCD device uses a vertical electric field that is perpendicular to the substrates, however, the AM-LCD device has poor viewing angles.
An in-plane switching (IPS) mode LCD device having a wide viewing angle property has been suggested and developed to resolve the above-mentioned limitations.
FIG. 1 is a cross-sectional view of a related art IPS mode LCD device. As shown in FIG. 1, the IPS mode LCD device includes an upper substrate 9 and a lower substrate 10 spaced apart from and facing each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9 and 10. A common electrode 17 and a pixel electrode 30 are formed on the lower substrate 10. The common electrode 17 and the pixel electrode 30 may be disposed on the same level. Liquid crystal (LC) molecules of the liquid crystal layer 11 are driven by a horizontal electric field L, which is induced between the common and pixel electrodes 17 and 30. Although not shown in the figure, a color filter layer is formed on the upper substrate 9. The upper substrate 9 including the color filter layer may be referred to as a color filter layer. The lower substrate 10 including the common electrode 17 and the pixel electrode 30 may be referred to as an array substrate.
FIGS. 2A and 2B are cross-sectional views showing turned on/off conditions, respectively, of a related art IPS mode LCD device. As shown in FIGS. 2A and 2B, when the voltage is applied to the IPS mode LCD device, arrangement of liquid crystal molecules 11a above the common electrode 17 and the pixel electrode 30 is unchanged. However, liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 are horizontally arranged due to the horizontal electric field L. Since the liquid crystal molecules 11b are arranged by the horizontal electric field L, the IPS mode LCD device has a wide viewing angle property. For example, the IPS mode LCD device has viewing angles of about 80 degrees to about 85 degrees up and down and right and left without an image inversion or a color inversion.
FIG. 2B shows a condition when the voltage is not applied to the IPS mode LCD device. Because an electric field is not induced between the common and pixel electrodes 17 and 30, the arrangement of liquid crystal molecules 11 of the liquid crystal layer is not changed.
Despite the advantages of the IPS mode LCD device described above, however, this device has disadvantages of low aperture ratio and transmittance. To improve the aperture ratio and transmittance of the IPS mode LCD device, a fringe field switching (FFS) mode LCD device has been suggested.
FIG. 3 is a plan view of a pixel region of an array substrate for a related art FFS mode LCD device.
As shown in FIG. 3, a gate line 43 is formed along a direction, and a data line 51 crosses the gate line 43 to define a pixel region P.
A thin film transistor Tr, as a switching element, is formed at the pixel region P and is connected to the gate line 43 and the data line 51. The thin film transistor Tr includes a gate electrode 45, a gate insulating layer (not shown), a semiconductor layer (not shown), and source and drain electrodes 55 and 58.
A pixel electrode 60 is formed at the pixel region P and is electrically connected to the drain electrode 58 of the thin film transistor Tr through a drain contact hole 59. The pixel electrode 60 has a plate shape.
A common electrode 75 is formed substantially all over a display area including a plurality of pixel regions P and includes openings oa corresponding to each pixel region P. The openings oa has a bar shape and are spaced apart from each other. Here, even though the common electrode 75 is formed substantially all over the display area, for the convenience of explanation, the common electrode 75 is indicated by a dashed line corresponding to the pixel region P.
In the array substrate of the related art FFS mode LCD device having the above-mentioned structure, a voltage is applied to the pixel electrode 60 having a plate shape and the common electrode 75 having the bar-shaped openings oa in the pixel region, and a fringe field is induced therebetween.
The array substrate for the related art FFS mode LCD device has been commonly manufactured through 6 mask processes as shown below.
FIGS. 4A to 4F are cross-sectional views of an array substrate for a related art FFS mode LCD device during the steps of fabrication according to the related art.
In FIG. 4A, a metal material layer (not shown) is formed on a substrate 40 and is patterned through a mask process, which includes applying photoresist, exposing the photoresist to light, developing the light-exposed photoresist, etching the metal material layer, and stripping the photoresist, to thereby form a gate electrode 43 on a switching area TrA, a gate line (not shown), and a gate pad electrode 44 on a gate pad area GPA. The gate line extends along a direction, and the gate electrode 43 and the gate pad electrode 44 are connected to the gate line. FIG. 4A also shows a data pad area DPA of the LCD device.
In FIG. 4B, a gate insulating layer 46 is formed on the gate line and the gate electrode 43, and subsequently an intrinsic amorphous silicon layer (not shown) and an impurity-doped amorphous silicon layer (not shown) are formed on the gate insulating layer 46. The intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer are patterned through a mask process to thereby form an active layer 49a and an impurity-doped amorphous silicon pattern 48 on the gate insulating layer 46 corresponding to the gate electrode 43.
Next, in FIG. 4C, a transparent conductive material is deposited on a substantially entire surface of the substrate 40 including the active layer 49a and the impurity-doped amorphous silicon pattern 48 and is patterned through a mask process to thereby form a pixel electrode 50 in the pixel region P.
In FIG. 4D, a metal layer (not shown) is formed on the pixel electrode 50 and the impurity-doped amorphous silicon pattern 48 of FIG. 4C and is patterned to thereby form a data line 52, a data pad electrode 53, and source and drain electrodes 54 and 56. The data line 52 crosses the gate line (not shown). The data pad electrode 53 is connected to the data line 52. The source and drain electrodes 54 and 56 are spaced apart from each other over the impurity-doped amorphous silicon pattern 48 of FIG. 4C. The source electrode 54 is connected to the data line 52. One end of the drain electrode 56 is extended onto the pixel electrode 50 and contacts the pixel electrode 50.
Then, the impurity-doped amorphous silicon pattern 48 of FIG. 4C exposed between the source and drain electrode 54 and 56 is removed to thereby form ohmic contact layers 49b, which are spaced apart from each other under the source and drain electrodes 54 and 56, respectively. Here, the active layer 49a and the ohmic contact layers 49b constitute a semiconductor layer 49. The gate electrode 43, the gate insulating layer 46, the semiconductor layer 49, and the source and drain electrodes 54 and 56 form a thin film transistor Tr.
In FIG. 4E, a passivation layer 60 is formed on the data line 52 and the source and drain electrodes 54 and 56 and is patterned to thereby form gate and data pad contact holes 62 and 64 exposing the gate and data pad electrodes 44 and 53, respectively.
Next, in FIG. 4F, a transparent conductive material layer (not shown) is formed on the passivation layer 60 including the gate and data pad contact holes 62 and 64 by depositing a transparent conductive material and is patterned through a mask process to thereby form a common electrode 65. The common electrode 65 includes bar-shaped openings oa corresponding to the pixel electrode 50 in the pixel region P. Accordingly, the array substrate for the FFS mode LCD device according to the related art is completed.
As shown above, the array substrate according to the related art is manufactured through 6 mask processes, and each mask process includes steps of applying photoresist, exposing the photoresist to light through a photo-mask, developing the light-exposed photoresist, etching a material layer, and stripping the photoresist. As the number of mask processes increases, the manufacturing time is lengthened, the productivity per unit time is lowered, and the manufacturing costs are raised. Therefore, an improved array substrate requiring fewer mask processes is desired.
Moreover, recently, as the display device has a large size, the signal lines become longer, and there is a problem of signal delays due to the resistance of the signal lines. Thus, an improved array substrate with less resistance of the signal lines is also desired.